The present invention relates generally to input/output (I/O) devices in integrated circuits, and more specifically to the testing of I/O devices in integrated circuits.
As integrated circuits become faster, they also become harder to test. Timing characteristics of I/O devices are one example of integrated circuit timing parameters that become more difficult to test as integrated circuits becomes faster. I/O devices have traditionally been tested by coupling a component tester to the integrated circuit to test I/O device timing parameters. Clock-to-output times (Tco) are measured by sampling an output signal for valid data and measuring a time distance between the clock signal and the valid data. Data setup times (Tsu) are measured by providing valid data at various times relative to a known clock signal. The precision with which these tests are performed are limited in part by the timing uncertainties of the component tester. Some I/O devices are becoming so fast that timing uncertainties in component testers represent an unacceptably large percentage of the total time budgeted, and the component tester causes otherwise good parts to fail tests.
FIG. 1 shows a prior art integrated circuit and component tester. Integrated circuit 100 includes data-out latch 102, output driver 104, signal pad 110, input receiver 108, and data-in latch 106. Data-out latch 102 and output driver 104 form the data output path for output data on node 116 to reach signal pad 110. Output data 116 is sourced by circuits internal to integrated circuit 100, and signal pad 110 provides access off of integrated circuit 100. Tco is measured as the time between the assertion of the front side bus clock on node 120 and valid data appearing on signal pad 110. Tco is shown by arrow 112 in FIG. 1. Input receiver 108 and data-in latch 106 form the input path for input data traveling from signal pad 110 to input data node 118. Tsu is measured as the minimum necessary time between valid data appearing on signal pad 110 and the assertion of the front side bus clock on node 120. Tsu is shown in FIG. 1 by arrow 114.
Coupled to integrated circuit 100 is component tester 130. Component tester 130 receives output data from signal pad 110, and sources input data to signal pad 110. Component tester 130 typically includes timing uncertainties, and these timing uncertainties are taken into account when designing tests. Timing tests typically include a timing budget that allocates a maximum timing error to the component tester. The prior art system of FIG. 1 works well when timing uncertainties within component tester 130 represent a very small amount of the timing budget. In contrast, when timing uncertainties within the component tester represent a large amount of the timing budget, it becomes difficult to design an effective test. For the fastest available integrated circuits today, many component testers have timing uncertainties that exceed allowable limits as specified in timing budgets.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved methods and apparatus to test fast integrated circuits.